The present invention relates generally to multi-layer capacitor arrays, and methods of manufacturing such arrays. In particular, the invention relates to capacitor arrays in which a plurality of capacitor units are arranged in high density for maximum efficiency while occupying a minimum amount of space on the surface of a circuit board.
High density mounting of electronic components on circuit boards is common in the electronics industry. Miniature ceramic capacitors having multiple layers have been used for some time in electronic devices such as cellular telephones, network routers, computers, and the like. The manufacturing techniques of such devices must be precise to provide for the greatly reduced size of these devices, while still affording desirable electrical operating characteristics.
Several United States patents are directed to various aspects of electronic component manufacture. For example, U.S. Pat. No. 5,548,474 is directed to methods of manufacture of capacitors. The following patents also relate to such electronic components and methods of manufacture: U.S. Pat. Nos. 5,565,838; 3,117,365; 3,538,571; 3,617,834; 3,635,759; and 4,574,438. U.S. Pat. No. 5,880,925 is directed to a multilayer ceramic device suitable for use in surface mount decoupling applications which may utilize a single capacitor or a capacitor array. The above referenced patents are hereby incorporated by reference into this disclosure as if fully set forth herein.
For some time, the design of various electronic components has been driven by a general industry trend toward miniaturization. In this regard, a need exists for smaller electronic components having exceptional operating characteristics. For example, some applications require a large capacitance value, but are severely limited in the amount of space (known as xe2x80x9creal estatexe2x80x9d) such a capacitor may occupy on a circuit board.
Multi-layer ceramic devices, sometimes referred to as xe2x80x9cmulti-layer ceramic capacitorsxe2x80x9d or xe2x80x9cMLCC""sxe2x80x9d usually are constructed with a plurality of ceramic-electrode layers arranged in a stack. During manufacture, the layers are pressed and formed into a vertically stacked structure. MLCC""s may have a single capacitor on a chip, or may include several capacitors in an array.
With the desire to increase functionality and reduce the size of such components, manufacturers are looking for new ways to provide varying (i.e. multiple) capacitance values in microcircuits. However, as the size of capacitors decreases, the dead space or spacing that must exist between capacitors when mounted on a circuit board becomes more and more important as a limiting factor in miniaturizing a design.
Thus, such capacitors typically have one pre-set capacitance value that cannot later be altered. Modernly, manufacturers are seeking ways to reduce the size and increase the flexibility of capacitor arrays. An array is a unit comprised of multiple capacitors. A significant limitation of current designs is that many currently known arrayed capacitors, once installed and constructed in the chip, are not variable as to their value (i.e.: the degree to which they can hold a charge).
A capacitor array having capacitors of varying value within a single chip would be highly desirable. Thus, a capacitor array design providing board manufacturers and assemblers more flexibility by affording multiple capacitance values on a single chip would be desirable. Further, an array design that can achieve these objectives while also conserving space on a circuit board would be highly desirable.
The present invention recognizes various disadvantages of prior art constructions and methods. Accordingly, it is one purpose of the present invention to provide various novel arrangements for the structure of a capacitor device.
It is a further object of the present invention to provide novel structural arrangements for a multi-layer ceramic capacitor array.
It is a further object of the present invention to provide a multi-layer ceramic capacitor having dual value arrays in which the array is formed using a process in which some of the capacitors in the array are formed on a first screen head, while other capacitors in the array are formed on a separate screen head. The construction of a capacitor in this way provides an opportunity to have multiple capacitance values within the same capacitor array.
Some of these objects are achieved by a capacitor device comprising a device body defined by a plurality of first layers and a plurality of second layers arranged in a stack. The layers are constructed of a capacitor material, such as a barium titanate. The capacitor device further includes a plurality of terminal structures electrically connected to the electrode plates in a predetermined manner.
The invention provides for a novel internal construction to achieve different capacitance values within the various elements of the chip. As one example, the device may integrate two or more different capacitance values into one standard capacitor array. A multitude of combinations are possible, including various combinations of the number of capacitors within the array, and also the value of each capacitor in farads or microfarads. The geographic location of a given capacitance value in a given array may be predetermined and selected to comply with a given manufacturing need on the surface of a circuit board. Thus, using this invention it is possible to custom manufacture capacitors for a given need on a given circuit board design, resulting in exactly the capacitance values needed, in exactly the order or location in which they are needed, while using a minimum amount of board space while doing so.
In the invention, an array is provided, comprising a first capacitor, the first capacitor having a first set of capacitor plates. Further, the first capacitor is usually capable of storing a predetermined electrical charge having a first value. Also provided is a second capacitor, the second capacitor comprising a second set of capacitor plates and also capable of storing a predetermined electrical charge having a second value. The second value may be about the same as the first value, or may be many orders of magnitude different from the first value. In many embodiments, the first value and the second value will be quite different. The capacitor array also may include capacitor plates of the first capacitor and the capacitor plates of the second capacitor which are formed by combining alternating layers of dielectric and conductive materials.
In some embodiments, the capacitor array may comprise a third capacitor having a third set of capacitor plates, the third capacitor being capable of storing a predetermined electrical charge having a third value. Still another alternative embodiment utilizes a fourth capacitor, the fourth capacitor comprising a fourth set of capacitor plates, the fourth capacitor being capable of storing a predetermined electrical charge having a fourth value. There is no practical limit to the number of capacitors that may be provided in the array of this invention. Arrays having five, six, seven, eight, or more capacitors may be employed, depending upon the circuit board application.
Although virtually any useful ordering or arrangement of capacitors may be employed, one common arrangement of a capacitor array having four capacitors is as follows: the two xe2x80x9couterxe2x80x9d capacitors on the end of the array are of about the same value, while the two xe2x80x9cinnerxe2x80x9d capacitors are of another distinct and separate value. In this particular embodiment, therefore, there is a xe2x80x9cdualxe2x80x9d or two value capacitor array in which two distinct capacitance values are provided on the chip (two capacitors per value in this instance). Of course, a multitude of other combinations are possible, especially as the number of capacitors on the chip increases. In some embodiments, an array is provided which has a first capacitance value and a second capacitance value that differ from each other by at least a factor of 10. In other embodiments, the capacitance values within a single array may differ by a factor of 100 or more.
In one embodiment of the invention, a capacitor array is provided in which the first set of capacitor plates of the first capacitor and the second set of capacitor plates of the second capacitor are formed using more than one screen head in a typical wet stacking process. Further, the capacitor array may be provided in which the first set of capacitor plates comprise at least a first top plate and a first bottom plate, the second set of capacitor plates comprise at least a second top plate and a second bottom plate, wherein the first top plate and the second top plate are not aligned at the same vertical level within the array. It is common to provide a capacitor array in which plates of the first capacitor and plates of the second capacitor are provided at different vertical levels in the array by applying conductive material and dielectric in multiple layers during manufacture.
In the arrangement of capacitors in the array, a designation scheme may be used in which letters xe2x80x9cAxe2x80x9d, xe2x80x9cBxe2x80x9d, and xe2x80x9cCxe2x80x9d and so forth are used to represent capacitors that are alike in their capacitance value. Thus, the ordering and the capacitance value of capacitors may be provided wherein the array may be represented by the designation ABBBA, for example. This xe2x80x9cABBBAxe2x80x9d embodiment indicates an array having five capacitors in which the two capacitors at each end of the array (i.e. xe2x80x9cAxe2x80x9d capacitors) are of one specific capacitance value, while the three capacitors in the center of the array are of another different value, designated as xe2x80x9cBxe2x80x9d. In another embodiment, an array of five capacitors may be provided by the designation ABABA, or alternatively AABAA. Other arrangements are possible as well.
In a four capacitor array, there are several possibilities, including: AAAA, ABBA, AABB, AAAB, ABAA, ABAB and the like.
In other embodiments of the invention, an electrical circuit board is presented with capacitor arrays attached to the board, in a generally planar board having on its surface a plurality of electrical current paths. Further, a capacitor array is provided comprising a first capacitor, the first capacitor comprising a first set of capacitor plates with dielectric between the plates, the first capacitor being capable of storing a predetermined electrical charge having a first value. Additionally, a second capacitor is provided, the second capacitor having a second set of capacitor plates with dielectric between the plates, the second capacitor being capable of storing a predetermined electrical charge having a second value. In some embodiments, there also is provided in the array a third capacitor, the third capacitor comprising a third set of capacitor plates with dielectric between the plates. The third capacitor is capable of storing a predetermined electrical charge having a third value. A fourth capacitor with a fourth set of capacitor plates with dielectric between the plates, the fourth capacitor being capable of storing a predetermined electrical charge having a fourth value. Other variations are possible as well.
Additionally, a method of making a capacitor array is disclosed which comprises providing a plurality of layers of dielectric material. Further, a plurality of layers of conductive material also are provided, the conductive material being located generally between layers of dielectric material. Then, the conductive material is hardened to form conductive plates, the conductive plates being adapted for interconnection to each other or to terminations capable of communicating with a circuit board. Then, the layers are stacked with dielectric material and conductive plates in a predetermined arrangement. In the method, the spacing of the conductive plates is provided to facilitate an appropriate capacitance value between the plates. Next, a first capacitor is formed, the first capacitor comprising a first set of capacitor plates, the first capacitor being capable of storing a predetermined electrical charge having a first value. A second capacitor is formed having a second set of capacitor plates, the second capacitor being capable of storing a predetermined electrical charge having a second value. Other methods employing three, four, five, six, or more capacitors in the array are possible, with a multitude of combinations of capacitance value and location on the array being possible.
In one embodiment of the invention, a resistor array, rather than a capacitor array, is provided, having a first resistor, the first resistor comprising a first set of plates, the first resistor being capable of resisting an electrical charge by an amount having a first value, and also a second resistor, the second resistor comprising a second set of resistor plates, the second resistor being capable of resisting an electrical charge by an amount having a second value.
In one embodiment of the invention, a varistor (voltage dependent resistor) array is provided, comprising a first varistor, the first varistor comprising a first set of plates, the first varistor being capable of absorbing a voltage transient of an electrical charge by an amount having a first value. Further, a second varistor is also part of the array, the second varistor comprising a second set of plates, the second varistor being capable of absorbing a voltage transient of an electrical charge by an amount having a second value.
A full and enabling disclosure of the present invention, including the best mode thereof, to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying drawings provided in this specification. It is to be recognized, however, that the drawings show representative examples but do not limit the number of combinations and sub-combinations that may be possible in application of this invention in a manner consistent with the written description.